Ryzen 8950X Zen 5 CPU Benchmark Scores Allegedly Break Cover And They're Really Good

erek

erek

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Hmm

“After delivering the benchmarks, RGT talked a bit about what he's heard concerning the Ryzen 8000 series CPUs as well as the Zen 5 processor cores. The previous 10-15% IPC expectation came from a CPU core design internal roadmap leaked by fellow YouTuber Moore's Law is Dead. Those numbers, according to RGT, were based on SPECint benchmarks, specifically, and Zen 5 is actually considerably faster in workloads that mix integer and floating-point math. That could be due to the increased dispatch width (from 6 to 8 instructions) on Zen 5.

Additionally, he says that the processor design philosophy at AMD has shifted significantly toward its high-margin EPYC CPU business. As a result, the processors are being designed with a lesser emphasis on single-threaded CPU clock and a greater emphasis on multi-threaded clocks, meaning that the gap between the two has shrunk. Good for creators and scientists; not great for gamers, although hardcore PC gamers should probably be considering an X3D processor anyway, and those already run lower clocks.”

https://hothardware.com/news/zen5-cpu-benchmark-rumor
 
Nice to hear that they are making progress.

Bummer to hear that single threaded performance is being de-emphasized.

As the old saying goes, multi-threader performance benefits some workloads while single threader performance benefits all workloads.

That said, this should be expected as we start to hit the wall of silicone.

All of that said, ever since sitting through 6 months to a year of "Bulldozer is going to change the CPU world and be the most amazing thing since sliced bread" leaks here in 2010-2011, only to have it come out as a huge flop, I take any information that comes out other than hard benchmarks with a truckload of salt.
 
Zarathustra[H] said:
Nice to hear that they are making progress.

Bummer to hear that single threaded performance is being de-emphasized.

As the old saying goes, multi-threader performance benefits some workloads while single threader performance benefits all workloads.

That said, this should be expected as we start to hit the wall of silicone.

All of that said, ever since sitting through 6 months to a year of "Bulldozer is going to change the CPU world and be the most amazing thing since sliced bread" leaks here in 2010-2011, only to have it come out as a huge flop, I take any information that comes out other than hard benchmarks with a truckload of salt.
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like this, right?

maxresdefault.jpg
 
16 zen5 core + 40 rdna 3.5 core laptop could be quite wilde, will be interesting to see against the M3.
 
While its nice to see some uplift in even single threaded workloads, I do hope they have not given up focusing on that regard as well. It may be some years before developers start to really start expecting more heavily multithreaded CPUs as a default and of course, not all kinds of workloads are easily parallelized . I'm a bit disappointed if, especially if this is their focus going forward, they (at least on the ES chips discussed) have not overhauled the memory controller but perhaps more importantly I would have liked to see some on-die scheduler-related factor the way that Intel does with their heterogenous P/E core chips.

Of course, one of the biggest issues I want them to deal with in the 8-series is regarding the X3D chips. Despite how high performance the 7950X3D is when everything goes "right", it launched with major impediments to this because of its heterogeneous design with some cores having extra VCache yet lower clocks, and some cores having the equivalent clocks of a 7950X but no VCache locally (though it could in theory borrow the cross-CCD cache, in practice this would be a scheduling nightmare without proper guidance on what circumstances it was wise). I would HOPE that by the 8000 series (which I am guessing will not debut until early 2024; I hope they do not delay the launch of their high end parts) they will be able to fix these potential issues by either A) placing extra VCache on both CCDs when it comes to the 8950X3D and ideally B) Finally resolving the temperature and bondng issue materials problems that will allow the stacked VCache to tolerate the same frequencies as the chip itself; identified during the 5000 series this was supposed to be ironed out with the delay for the 7000 and clearly progress was made, but not quite enough. Hopefully by 8000 they will have it sorted.

Even if they do manage the above, the heterogeneous chip design focus will not be going away as from all sides we have the Intel P/E cores, AMD's VCache and Zen4c etc... so even should there be no on-die feature, would like to see AMD put serious work into firmware, OS, and software alike, ideally open source, to ensure that scheduling, regardless of OS, can thrive and balance the optimal workload to take advantage of the hardware.
 
RanceJustice said:
While its nice to see some uplift in even single threaded workloads, I do hope they have not given up focusing on that regard as well. It may be some years before developers start to really start expecting more heavily multithreaded CPUs as a default and of course, not all kinds of workloads are easily parallelized . I'm a bit disappointed if, especially if this is their focus going forward, they (at least on the ES chips discussed) have not overhauled the memory controller but perhaps more importantly I would have liked to see some on-die scheduler-related factor the way that Intel does with their heterogenous P/E core chips.

Of course, one of the biggest issues I want them to deal with in the 8-series is regarding the X3D chips. Despite how high performance the 7950X3D is when everything goes "right", it launched with major impediments to this because of its heterogeneous design with some cores having extra VCache yet lower clocks, and some cores having the equivalent clocks of a 7950X but no VCache locally (though it could in theory borrow the cross-CCD cache, in practice this would be a scheduling nightmare without proper guidance on what circumstances it was wise). I would HOPE that by the 8000 series (which I am guessing will not debut until early 2024; I hope they do not delay the launch of their high end parts) they will be able to fix these potential issues by either A) placing extra VCache on both CCDs when it comes to the 8950X3D and ideally B) Finally resolving the temperature and bondng issue materials problems that will allow the stacked VCache to tolerate the same frequencies as the chip itself; identified during the 5000 series this was supposed to be ironed out with the delay for the 7000 and clearly progress was made, but not quite enough. Hopefully by 8000 they will have it sorted.

Even if they do manage the above, the heterogeneous chip design focus will not be going away as from all sides we have the Intel P/E cores, AMD's VCache and Zen4c etc... so even should there be no on-die feature, would like to see AMD put serious work into firmware, OS, and software alike, ideally open source, to ensure that scheduling, regardless of OS, can thrive and balance the optimal workload to take advantage of the hardware.
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Temperature bonding issues are gonna be tough as the CoWoS packaging TSMC uses does have a low melting point for the copper bond that makes up their TSVs.
I would hope for better thread core allocations on something like an 8950 for sure but I doubt we would see a case where 2 CCD's have the extra cache as it would be utterly wasted and it wouldn't serve the intended purpose.

Games don't thread out to 16/32, they barely thread out to 8/16, the 7950 was intended for people who have some prosumer workloads but also like to game on their hardware, and the lower clock speeds of the X3D would hinder that as a whole.

AMD is better off just leaving the X3D on a single CCD for the time being, I am hoping to see some better options for the Memory controller though I am tired of being limited to 2 channels on consumer hardware, having access to 4 would be idea but I would happily accept 3 as a concession. Even if that meant going to 3/6 DIMM configurations again, because it's obvious based on how clock speeds affect gaming that we are being channel starved there.
 
Lakados said:
Temperature bonding issues are gonna be tough as the CoWoS packaging TSMC uses does have a low melting point for the copper bond that makes up their TSVs.
I would hope for better thread core allocations on something like an 8950 for sure but I doubt we would see a case where 2 CCD's have the extra cache as it would be utterly wasted and it wouldn't serve the intended purpose.

Games don't thread out to 16/32, they barely thread out to 8/16, the 7950 was intended for people who have some prosumer workloads but also like to game on their hardware, and the lower clock speeds of the X3D would hinder that as a whole.

AMD is better off just leaving the X3D on a single CCD for the time being, I am hoping to see some better options for the Memory controller though I am tired of being limited to 2 channels on consumer hardware, having access to 4 would be idea but I would happily accept 3 as a concession. Even if that meant going to 3/6 DIMM configurations again, because it's obvious based on how clock speeds affect gaming that we are being channel starved there.
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Leaked Flyer Hints at Possible AMD Ryzen 9000 Series Powered by Zen 5​

by AleksandarK Today, 11:17 Discuss (7 Comments)
A curious piece of marketing material on the Chiphell forum has sent ripples through the tech community, featuring what appears to be an Alienware desktop equipped with an unannounced AMD Ryzen 9000-series processor. The authenticity of this flyer is up for debate, with possibilities ranging from a simple typo by Alienware to a fabricated image, or it could even suggest that AMD is on the cusp of unveiling its next-generation Ryzen CPUs for desktop PCs. While intrigue is high, it's important to approach such revelations cautiously, with a big grain of salt. AMD's existing roadmap points toward a 2024 release for its Zen 5-based Ryzen desktop processors and EPYC server CPUs, which casts further doubt on the Ryzen 9000 series appearing ahead of schedule.

We have to wait for AMD's major upcoming events, including the "Advancing AI" event on December 6, where the company will showcase how its partners and AMD use AI for applications. Next, we hope to hear from AMD about upcoming events such as CES in January and Computex in May, but we don't have any official information on product launches in the near term. If the company is preparing anything, the Alienware flyer pictured below should indicate it, if the source is confirmed. However, the doubt remains, and we should be skeptical of its truthfulness.
 
erek said:

Leaked Flyer Hints at Possible AMD Ryzen 9000 Series Powered by Zen 5​

by AleksandarK Today, 11:17 Discuss (7 Comments)
A curious piece of marketing material on the Chiphell forum has sent ripples through the tech community, featuring what appears to be an Alienware desktop equipped with an unannounced AMD Ryzen 9000-series processor. The authenticity of this flyer is up for debate, with possibilities ranging from a simple typo by Alienware to a fabricated image, or it could even suggest that AMD is on the cusp of unveiling its next-generation Ryzen CPUs for desktop PCs. While intrigue is high, it's important to approach such revelations cautiously, with a big grain of salt. AMD's existing roadmap points toward a 2024 release for its Zen 5-based Ryzen desktop processors and EPYC server CPUs, which casts further doubt on the Ryzen 9000 series appearing ahead of schedule.

We have to wait for AMD's major upcoming events, including the "Advancing AI" event on December 6, where the company will showcase how its partners and AMD use AI for applications. Next, we hope to hear from AMD about upcoming events such as CES in January and Computex in May, but we don't have any official information on product launches in the near term. If the company is preparing anything, the Alienware flyer pictured below should indicate it, if the source is confirmed. However, the doubt remains, and we should be skeptical of its truthfulness.
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Could be interesting, I thought the 8000 series was pretty much confirmed though.

Who knows maybe they are going back to the mobile components being named different from the desktop ones of the same generation.
So the mobile parts will be 8000 and the desktop 9000, because we all loved it when AMD used to do that right?
 
Man, this is totally going to turn out to be a stupid typo. Dell's going to put next-next gen CPU in the last-gen Alienware? Nah.
 
1_rick said:
Man, this is totally going to turn out to be a stupid typo. Dell's going to put next-next gen CPU in the last-gen Alienware? Nah.
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Awh shit yeah, that’s the R14-15 chassis, the R16 is rectangular again.
So that would be quite the step back.
Not sure how I didn’t catch that one, good eye!
I’m thinking R14 because that’s when all their marketing was Red and Black, the 15 then went White and Blue.
 
RanceJustice said:
While its nice to see some uplift in even single threaded workloads, I do hope they have not given up focusing on that regard as well. It may be some years before developers start to really start expecting more heavily multithreaded CPUs as a default and of course, not all kinds of workloads are easily parallelized .
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I tend to be of the opinion that most things that can benefit from multithreading have already been multitgreaded as far as they are going to go at this point.

It's a distinct minority of code that is even possible to be multitgreaded.
 
Zarathustra[H] said:
I tend to be of the opinion that most things that can benefit from multithreading have already been multitgreaded as far as they are going to go at this point.

It's a distinct minority of code that is even possible to be multitgreaded.
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Games get weird when you split them off into lots of threads, because of all the interrupts and all the things that interact it is very easy to enter miniature deadlock states which cause studdering and frame drops or just weird glitches.
One of the bigger problems is the limited number of memory channels in consumer systems, with only 2 channels only 2 threads can communicate with system memory at a given time, and god forbid that 2 threads need to communicate with each other, so the more threads you branch out the more chances for one of them needing to wait for memory access, so you quickly approach a point of diminishing returns.
AMD tackles this on the x3Ds with the huge amount of cache which limits the number of times the cores need to access memory and the fact it works so well there shows 2 things, AMD needs a better memory controller, and we need more memory channels. But it is a great, though inconvenient stopgap.
DDR5 can help tackle this with its channel-splitting capabilities, but there isn't enough of it out in the wild for game engines to be optimized to take advantage of that yet, and by the time there is we'll probably be on DDR6.

Threading can be expanded out under the right circumstances, one of which is introducing frame caps which the PC community overwhelmingly hates so that's not really a good idea.
This of course isn't true for all game types, turn-based ones for instance can be multi-threaded extremely well as it is the AI that takes up the bulk of the processing there, but you don't exactly go chasing frame rates in those.
 
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Lakados said:
Could be interesting, I thought the 8000 series was pretty much confirmed though.

Who knows maybe they are going back to the mobile components being named different from the desktop ones of the same generation.
So the mobile parts will be 8000 and the desktop 9000, because we all loved it when AMD used to do that right?
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It's being said that the Zen4 APUs (already released as 7040-series on mobile) will be branded as 8000-series in their AM5 desktop versions (Videocardz Sauce). That could suggest desktop Zen5 will be 9000-series instead... unless AMD decides to bring to the desktop their complicated-ass mobile naming scheme where "7000 series" includes 7020 Zen2, 7030 Zen3, and 7040 Zen4 parts- which, ugh, I'd rather they don't do that. I don't see how it's so complicated to have a consistent naming scheme... It seemed like they'd made a correction in 2020/21 with all Zen3 CPU and APU named as 5000 series across desktop and mobile, but I guess that made too much sense! /rant
 
Lakados said:
Temperature bonding issues are gonna be tough as the CoWoS packaging TSMC uses does have a low melting point for the copper bond that makes up their TSVs.
I would hope for better thread core allocations on something like an 8950 for sure but I doubt we would see a case where 2 CCD's have the extra cache as it would be utterly wasted and it wouldn't serve the intended purpose.

Games don't thread out to 16/32, they barely thread out to 8/16, the 7950 was intended for people who have some prosumer workloads but also like to game on their hardware, and the lower clock speeds of the X3D would hinder that as a whole.

AMD is better off just leaving the X3D on a single CCD for the time being, I am hoping to see some better options for the Memory controller though I am tired of being limited to 2 channels on consumer hardware, having access to 4 would be idea but I would happily accept 3 as a concession. Even if that meant going to 3/6 DIMM configurations again, because it's obvious based on how clock speeds affect gaming that we are being channel starved there.
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I was under the impression that they completely changed the material from the 5800X3D to the 7000-series X3Ds to allow for higher temperature durability in the bonding of stacked cache, but clearly even that is an improvement yet an incomplete solution if there is a limitation of temp or clocks required vs the standard CCD unit. Do you think they cannot improve the process or materials further in the next generation, as they did with this one over the previous?

As far as better thread allocations, that's something I definitely wish to see but in the event that they didn't have such such variation between cores in semi-complex manner (ie as opposed to say, the Zen4c cores which should be easier for scheduler allocation given they're simply lower power and run slower, so simple rules like "prefer those capable of turbo boosting to the fastest limit first" can be used) that would also solve the issue. I remember that when discussing the 7900X3D/7950X3D some thought hypothetically its asymmetric layout would be an outmoded compromise by the next generation, which could explain why they didn't exactly go all in for scheduler performance despite it being a top of the line processor when all was working as it should. As far as having cache on both CCDs, I imagine that would be a situation where it did not require a reduction in clock speed and thus could be available for any workloads that needed it, regardless. Indeed, I also felt the 7950X3D was designed for best of both worlds gaming and prosumer workloads, assuming optimal scheduling and performance; a reason I was so surprised for them to , at least at launch, use such an insufficient solution for workload assignment as the Windows Game Bar = Prefer Cache setup. However, a mixed use gaming + prosumer workload would be even more capable on a 8000/9000 series halo chip w/ 16c/32t extra cache and maximal clockspeed capability on both CCDs; if it could be done, of course.

Definitely onboard with needing an upgraded memory controller. As a HEDT owner for the X58 - X99 chipset era, I'd be more than comfortable with a tri- or quad-channel option. Especially given how it seem that the "gaming/mixed used HEDT" plaforms from both Intel and AMD have been outmoded in favor of "MOAR CORES, server and workstation junior HEDT" setups , I think it would be nice if they could expand Ryzen chipset compatibility in terms of both memory channels and PCI-E lanes. I'm glad that you can get overall the kind of 8 or even 16 core CPUs that a few generations ago you'd need HEDT to even approach, but it did some with some limitations. If they offered some sort of X670EX (or X770EX) chipset that would support quad channel RAM and additional PCI-E lanes it would let those who didn't need that to stick with dual channel and the standard amount of PCI-E lanes?
 
RanceJustice said:
I was under the impression that they completely changed the material from the 5800X3D to the 7000-series X3Ds to allow for higher temperature durability in the bonding of stacked cache, but clearly even that is an improvement yet an incomplete solution if there is a limitation of temp or clocks required vs the standard CCD unit. Do you think they cannot improve the process or materials further in the next generation, as they did with this one over the previous?

As far as better thread allocations, that's something I definitely wish to see but in the event that they didn't have such such variation between cores in semi-complex manner (ie as opposed to say, the Zen4c cores which should be easier for scheduler allocation given they're simply lower power and run slower, so simple rules like "prefer those capable of turbo boosting to the fastest limit first" can be used) that would also solve the issue. I remember that when discussing the 7900X3D/7950X3D some thought hypothetically its asymmetric layout would be an outmoded compromise by the next generation, which could explain why they didn't exactly go all in for scheduler performance despite it being a top of the line processor when all was working as it should. As far as having cache on both CCDs, I imagine that would be a situation where it did not require a reduction in clock speed and thus could be available for any workloads that needed it, regardless. Indeed, I also felt the 7950X3D was designed for best of both worlds gaming and prosumer workloads, assuming optimal scheduling and performance; a reason I was so surprised for them to , at least at launch, use such an insufficient solution for workload assignment as the Windows Game Bar = Prefer Cache setup. However, a mixed use gaming + prosumer workload would be even more capable on a 8000/9000 series halo chip w/ 16c/32t extra cache and maximal clockspeed capability on both CCDs; if it could be done, of course.

Definitely onboard with needing an upgraded memory controller. As a HEDT owner for the X58 - X99 chipset era, I'd be more than comfortable with a tri- or quad-channel option. Especially given how it seem that the "gaming/mixed used HEDT" plaforms from both Intel and AMD have been outmoded in favor of "MOAR CORES, server and workstation junior HEDT" setups , I think it would be nice if they could expand Ryzen chipset compatibility in terms of both memory channels and PCI-E lanes. I'm glad that you can get overall the kind of 8 or even 16 core CPUs that a few generations ago you'd need HEDT to even approach, but it did some with some limitations. If they offered some sort of X670EX (or X770EX) chipset that would support quad channel RAM and additional PCI-E lanes it would let those who didn't need that to stick with dual channel and the standard amount of PCI-E lanes?
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The application method for the stacked cache still requires the use of a metal based solder adhesive that is applied directly to the silicon, that means it’s melting and application temperatures need to be within the range where it can’t damage the silicon. Which sadly lands it inside the operating range of the chips. TSMCs CoWoS process was designed with mobile chips in mind things for cellphones and the like where the temperatures of a desktop or laptop CPU would be unthinkable.
TSMC has made some solid headway with the process but the methods themselves just don’t lend themselves to higher voltages.

AMDs c cores use a fundamentally different gate, normally x86 cores use an 8T SRam cell, it has better latency, is less prone to error, and is more stable as a whole. For the C cores AMD is using a 6T SRam cell structure, 25% smaller yes but less stable, prone to errors at high clocks, and can only process single word lines where 8T can handle 2 but you need to address them differently and how they behave is quite different as well. So the C cores have a bit more going on than just being slower less powerful cores. The shrink came at a cost, it will be very interesting to see how they perform in the wild though.

I really want more consumer memory channels, my playtime workloads don’t need PCIe lanes but 2 memory channels hurt, 4 would be ideal but 3 would be a sizeable improvement. Games would improve a lot too but memory channels are one of the major gatekeepers between consumer and workstation hardwares and I don’t see either AMD or Intel giving that margin up any time soon.
 
NattyKathy said:
It's being said that the Zen4 APUs (already released as 7040-series on mobile) will be branded as 8000-series in their AM5 desktop versions (Videocardz Sauce). That could suggest desktop Zen5 will be 9000-series instead... unless AMD decides to bring to the desktop their complicated-ass mobile naming scheme where "7000 series" includes 7020 Zen2, 7030 Zen3, and 7040 Zen4 parts- which, ugh, I'd rather they don't do that. I don't see how it's so complicated to have a consistent naming scheme... It seemed like they'd made a correction in 2020/21 with all Zen3 CPU and APU named as 5000 series across desktop and mobile, but I guess that made too much sense! /rant
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The funny thing is, remember when they jumped the desktop from 3000 to 5000 to align the desktop and mobile numbers? Then they immediately threw that away with 6000-series mobile chips.
 
1_rick said:
The funny thing is, remember when they jumped the desktop from 3000 to 5000 to align the desktop and mobile numbers? Then they immediately threw that away with 6000-series mobile chips.
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Then brought them back into alignment with the 7000 series to possibly throw them away for the 8000?
 
1_rick said:
The funny thing is, remember when they jumped the desktop from 3000 to 5000 to align the desktop and mobile numbers? Then they immediately threw that away with 6000-series mobile chips.
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I may be mistaken, but didnt amd previously had chips that were same node and same architecture but had different series numbers? 6000 series was a node shrink from 5000 series right?
 
I was tempted to upgrade from my 5800X to a 7800X3D but I think I'm going to hold off until Zen 5...shouldn't be too much longer (June official reveal at Computex?)...the new architecture sounds impressive based on the leaks
 
I upgraded to zen 5 fairly early and while good it’s not an amazing leap for what I do with my machines. Basically they are hobby/ entertainment boxes. Ended up parting that system out. The 7800x3d is really the best and only choice for my use case when it comes down to it. Even so I’m not playing any games that aren’t easily handled by what I run now. Holding out is the plan here.
 
Bah! Yes typo.. Am5 was what I meant. Had a 7700x. Great cpu performance wise that was pissy with a couple of ram kits and two different mobos and I got sick if dealing with it. With all that said at this time AM5 is probably easy enough so maybe a 7800x3d on an itx board will replace my b550 5600x system at some point. Not in a hurry though the sale prices are getting decent!
 
I'm also waiting, Might get a 7xxx chip after zen5 is out, depending on how this shakes out.
 
RanceJustice said:
It may be some years before developers start to really start expecting more heavily multithreaded CPUs as a default and of course, not all kinds of workloads are easily parallelized
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In 2010 some programs would have not run well on a single thread cpu (the one I was working on around that time for example), the system would have shut down, it assumed the os and others had there threads.

The cheapest $400 Costco Laptop has a 10,000 multithread passmark like 12 core-24 threads Xeon 2648L had in the past, it has been more than a decade that people that start to make a program expect to be run on heavily multithreaded CPUs, the Q6600 launched in 2007.

The all kind of workload will have a single thread limitation showing up is more the issue I think.

PS just saw that this is a November article and calling fixing issue that make CPU not scale perfectly with core count goes away a de-emphasis on single thread performance is a bit of a negative way to present things.
 
I think were taking a bit out of context, they said they reduced focus on single core clock speed and focused on higher clock speeds for multithreaded. Which has worked out just fine for me on my 5800X3D. Honestly I just think they are hitting a wall on clock speed.
 
While my Ryzen 9 5900X is still going strong, saying I'm not tempted by the performance improvements of even the current 7000 series would be a lie. A few things I do/play would benefit from the clock and IPC increase. I might have to jump to a 9900X or 9900X3D if the numbers are that much better overall.
 
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I sit here and go mmm... my 1st gen x370 am4 has held me out quite well this long. I'm seriously considering an overhaul on everything soon enough but I'll hang into my rig, it's still hauling and pulling punches just fine.

And the 8000series are mouthwatering. I'm going to be looking at the 65w segment. It's my targeted preference but we'll have to wait and see what the line up looks to be and I'll go 2nd gen am5, dunno chipset but pretty comfortable that point in everything thing been mainly hashed out then.
 
Mr. Bluntman said:
While my Ryzen 9 5900X is still going strong, saying I'm not tempted by the performance improvements of even the current 7000 series would be a lie. A few things I do/play would benefit from the clock and IPC increase. I might have to jump to a 8900X or 8900X3D if the numbers are that much better overall.
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Are we assuming Zen5 desktop line will be 8000 and not 9000? I guess I was under the assumption that 8000 was going to be the Zen4 APU's only. If they used 8000 it would be horribly confusing.. though I guess I wouldn't be surprised.
 
criccio said:
Are we assuming Zen5 desktop line will be 8000 and not 9000? I guess I was under the assumption that 8000 was going to be the Zen4 APU's only. If they used 8000 it would be horribly confusing.. though I guess I wouldn't be surprised.
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I didn't have enough caffeine before posting that. Whoopsie! :p

Moving on... I wonder if they'll eventually do a dual v-cache part on mainstream desktop? I know AMD messed around with such a part internally for AM4, but for some reason decided against releasing one...
 
Mr. Bluntman said:
I didn't have enough caffeine before posting that. Whoopsie! :p

Moving on... I wonder if they'll eventually do a dual v-cache part on mainstream desktop? I know AMD messed around with such a part internally for AM4, but for some reason decided against releasing one...
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The frequency hit hurts production loads too heavily and games loose performance when splitting across CCXs.
So putting the extra cache on both is an overall loose loose while making the part both more expensive to buy and more difficult to produce.
 
Lakados said:
The frequency hit hurts production loads too heavily and games lose performance when splitting across CCXs.
So putting the extra cache on both is an overall lose-lose while making the part both more expensive to buy and more difficult to produce.
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Fair enough.
 
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