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erek
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Hmm 
“ChipNeMo is a single model that can take on three types of tasks, all of which are concerned with designer productivity and helping to use EDA tools more efficiently rather than actually performing chip design. The 43-billion-parameter ChipNeMo runs on a single Nvidia A100 GPU in “a few seconds,” Dally said.
ChipNeMo can answer questions about chip design, particularly from junior designers.
“It turns out our senior designers spend a lot of time answering questions from junior designers,” Dally said. “If the first thing the junior designer can do is to go to ChipNeMo and say, ‘What does this signal coming out of the memory unit do?’—and if they get a possible answer that saves the senior designer’s time, the tool is well worth it.”
To avoid hallucination, Nvidia used a technique called retrieval augmented generation (RAG).
“We use the initial prompt to query a database and pull up a bunch of source documents that are relevant to this particular query,” Dally said. “We can append it to the prompt and feed it to ChipNeMo so we can ground that response to particular source documents, which reduces the tendency to hallucinate and makes things more explainable.”
ChipNeMo can also summarize bugs that are already documented. Typical bug documentation needs to be exhaustive and can result in designers having to read long documents–even to get the basics of what the bug does.
“Bug summarization is probably the lowest-hanging fruit in getting productivity,” Dally said. “When there’s a bug filed, people throw all sorts of stuff into [our bug system]…the tool is pretty good at summarizing a bug down to a concise paragraph and then saying, here’s who should go try to fix it.”
Chip NeMo can also write short scripts (circa 20 lines of code is typical, Dally said) in Tcl, the industry standard scripting language used for EDA tools. Scripting is a typical way to interface with CAD tools.
Could EDA Tool vendors eventually use this technology as a higher level of abstraction for chip design? They could if they had access to the training data, Dally said.
“I could imagine that [EDA tool vendors] would be very interested in having [an LLM] be a more approachable human interface to the tool,” he said. “Writing scripts for a lot of these tools is an art, and if they could at least get a set of scripts for a particular tool and fine tune on that, then they could make it much easier for designers to use the tools because you could write in human language: ‘Here’s what I’d like the tool to do,’ and it would then generate the script that would direct the tool to do that.”
ChipNeMo is intended for Nvidia internal use only and will not be commercialized, though other chip companies may find success training LLMs on their own internal data, Dally said.
“[ChipNeMo] is fairly specialized to how Nvidia does things,” he said. “For example, we have a particular way of writing scripts and all the scripts that it’s seen are NVIDIA scripts, but that’s what we want, this is for internal use.”
While it likely learned a lot of generic chip-design concepts from being trained on GPU design, this would be broadly applicable to any type of digital chip design but with the particular style that Nvidia has developed over the years, Dally said.
While this technology is still currently a research project, it is being tested inside Nvidia to gather feedback from team members designing Nvidia’s future products. ChipNeMo will probably be applied to more use cases across the chip-design process in the future, Dally said.
“This tool can be applied to many stages of chip design, [perhaps] writing scripts to run logic simulations or test benches early in the process, or it could be scripts to do macro placement later on, or timing verification and rule checking in the final stages,” he said. “We’d like to do this because what limits us on designing chips is human resources: We want to give our designers ‘superpowers’ so that we can design more and better chips with the same designers, and that needs to apply throughout all the stages of the design process.””
https://www.eetimes.com/nvidia-trains-llm-on-chip-design/
“ChipNeMo is a single model that can take on three types of tasks, all of which are concerned with designer productivity and helping to use EDA tools more efficiently rather than actually performing chip design. The 43-billion-parameter ChipNeMo runs on a single Nvidia A100 GPU in “a few seconds,” Dally said.
ChipNeMo can answer questions about chip design, particularly from junior designers.
“It turns out our senior designers spend a lot of time answering questions from junior designers,” Dally said. “If the first thing the junior designer can do is to go to ChipNeMo and say, ‘What does this signal coming out of the memory unit do?’—and if they get a possible answer that saves the senior designer’s time, the tool is well worth it.”
To avoid hallucination, Nvidia used a technique called retrieval augmented generation (RAG).
“We use the initial prompt to query a database and pull up a bunch of source documents that are relevant to this particular query,” Dally said. “We can append it to the prompt and feed it to ChipNeMo so we can ground that response to particular source documents, which reduces the tendency to hallucinate and makes things more explainable.”
ChipNeMo can also summarize bugs that are already documented. Typical bug documentation needs to be exhaustive and can result in designers having to read long documents–even to get the basics of what the bug does.
“Bug summarization is probably the lowest-hanging fruit in getting productivity,” Dally said. “When there’s a bug filed, people throw all sorts of stuff into [our bug system]…the tool is pretty good at summarizing a bug down to a concise paragraph and then saying, here’s who should go try to fix it.”
Chip NeMo can also write short scripts (circa 20 lines of code is typical, Dally said) in Tcl, the industry standard scripting language used for EDA tools. Scripting is a typical way to interface with CAD tools.
Could EDA Tool vendors eventually use this technology as a higher level of abstraction for chip design? They could if they had access to the training data, Dally said.
“I could imagine that [EDA tool vendors] would be very interested in having [an LLM] be a more approachable human interface to the tool,” he said. “Writing scripts for a lot of these tools is an art, and if they could at least get a set of scripts for a particular tool and fine tune on that, then they could make it much easier for designers to use the tools because you could write in human language: ‘Here’s what I’d like the tool to do,’ and it would then generate the script that would direct the tool to do that.”
ChipNeMo is intended for Nvidia internal use only and will not be commercialized, though other chip companies may find success training LLMs on their own internal data, Dally said.
“[ChipNeMo] is fairly specialized to how Nvidia does things,” he said. “For example, we have a particular way of writing scripts and all the scripts that it’s seen are NVIDIA scripts, but that’s what we want, this is for internal use.”
While it likely learned a lot of generic chip-design concepts from being trained on GPU design, this would be broadly applicable to any type of digital chip design but with the particular style that Nvidia has developed over the years, Dally said.
While this technology is still currently a research project, it is being tested inside Nvidia to gather feedback from team members designing Nvidia’s future products. ChipNeMo will probably be applied to more use cases across the chip-design process in the future, Dally said.
“This tool can be applied to many stages of chip design, [perhaps] writing scripts to run logic simulations or test benches early in the process, or it could be scripts to do macro placement later on, or timing verification and rule checking in the final stages,” he said. “We’d like to do this because what limits us on designing chips is human resources: We want to give our designers ‘superpowers’ so that we can design more and better chips with the same designers, and that needs to apply throughout all the stages of the design process.””
https://www.eetimes.com/nvidia-trains-llm-on-chip-design/
