How We’ll Reach a 1 Trillion Transistor GPU

erek

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Advances in semiconductors …

“A Mead-Conway Moment for 3D Integrated Circuits
In 1978, Carver Mead, a professor at the California Institute of Technology, and Lynn Conway at Xerox PARC invented a computer-aided design method for integrated circuits. They used a set of design rules to describe chip scaling so that engineers could easily design very-large-scale integration (VLSI) circuits without much knowledge of process technology.

That same sort of capability is needed for 3D chip design. Today, designers need to know chip design, system-architecture design, and hardware and software optimization. Manufacturers need to know chip technology, 3D IC technology, and advanced packaging technology. As we did in 1978, we again need a common language to describe these technologies in a way that electronic design tools understand. Such a hardware description language gives designers a free hand to work on a 3D IC system design, regardless of the underlying technology. It’s on the way: An open-source standard, called 3Dblox, has already been embraced by most of today’s technology companies and electronic design automation (EDA) companies.

The Future Beyond the Tunnel​

In the era of artificial intelligence, semiconductor technology is a key enabler for new AI capabilities and applications. A new GPU is no longer restricted by the standard sizes and form factors of the past. New semiconductor technology is no longer limited to scaling down the next-generation transistors on a two-dimensional plane. An integrated AI system can be composed of as many energy-efficient transistors as is practical, an efficient system architecture for specialized compute workloads, and an optimized relationship between software and hardware.

For the past 50 years, semiconductor-technology development has felt like walking inside a tunnel. The road ahead was clear, as there was a well-defined path. And everyone knew what needed to be done: shrink the transistor.

Now, we have reached the end of the tunnel. From here, semiconductor technology will get harder to develop. Yet, beyond the tunnel, many more possibilities lie ahead. We are no longer bound by the confines of the past.”

Source: https://spectrum.ieee.org/trillion-transistor-gpu
 
Or....
https://www.cerebras.net/press-release/cerebras-announces-third-generation-wafer-scale-engine#:~:text=Cerebras Systems Unveils World's Fastest AI Chip with Whopping 4 Trillion Transistors,-Third Generation 5nm&text=SUNNYVALE, CALIFORNIA – March 13,,the Wafer Scale Engine 3.

Cerebras Systems Unveils World’s Fastest AI Chip with Whopping 4 Trillion Transistor

B200 being already a bit over 200 billions (GB200 platform will have 2 of those on them), M3 ultra around 184 billions, if the craze continue and the R&D budget market for the craziest affair at the craziest price we can it imagine it with more regular size die connected together soon enough, if they can connect 2 B100, we can imagine that they will be able to connect 4 and those will have by then maybe already enough transistor to flirt with the trillion.
 
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