Heh...
I'm just going to tell you up front you have no idea what you are talking about. IPC (or MIPS) are absolute.
Let's review your question exactly as you put it.
That's so damn general you could drive a bus through it.Ok.. so how many instructions per clock cycle does bulldozer do?
It was a rhetorical question because people throw around IPC without knowing what it is.
And I'm just going to tell you that you are trying to be facetious but don't know how to do it correctly, or were you being dishonest when you knew an answer? Essentially you are being too cute by half and hoping no one realizes it. What you are attempting to argue is that IPC is a strictly defined definition to mean only one thing and one thing only (max throughput and in your case any instruction type). This is not the case from a programmatic point of view, or real world workloads (this right here is why we test with them to begin with).
But in cause you are wondering, Bulldozer's integer instructions per clock cycle is 8.
Sure in a perfect world ( I seem to remember it being 4 though). If you were correct with your assertion with regards to software then no matter what compiler tuning was given upon compile we would always get the same result. We don't not even close. You are attempting to conflate IPC from max throughput of an architecture, and then go on to claim that it can be universally applied to every workload without taking into account, branch mispredicts, pipeline stalls, latency, bitness, or cache size. Sure it's 8 instructions per cycle but it isn't with shitty code, or code meant for another architecture. This is just not going to fly with anyone. I mean it's kind of cute, but demonstrably ignorant. The whole point of providing you with that link is to show that actual software that people use can affect any architecture's capability to achieve max throughput, especially when it came to BD.
No one believes that except you...like literally. Any chip without software is a paper weight. It's not processing a damn thing without it, nor will it understand how to process it without it.What software is involved is meaningless.
This much is very true. But that's not what you are arguing here. You also fail to realize that shitty code can have implications regardless of what should be possible.This is a hardware specification which has software *implications*.
Vague, but I thought you didn't know at all? Whoops. Ulterior motive alert!"Ricin" on the other hand has 16 instructions per clock cycle. Like the Intel chip used in the AMD demo.
Ignorance is bliss as they say. However, you might want to read some in depth analysis of any CPU architecture because all of it reviews max throughput against all of the different scenarios I listed above. It would do you some good that way when you figure you are going to be too cute by half with anyone maybe just maybe you will think twice.All you had to do was know what you were talking about- no Google needed
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