Anandtech: The Intel Lakefield Deep Dive: Everything To Know About the First x86 Hybrid CPU

[Snowdog]

Intel's Rube Goldberg Atom-Core Hybrid with multiple Layers, that performs like an Atom.

It looks like a lot more complexity (and thus cost) for a questionable benefit.

https://www.anandtech.com/show/15877/intel-hybrid-cpu-lakefield-all-you-need-to-know

 

[Absalom]

This isn't innovation. This is copycatting a soon-to-be competitor's already proven concepts and ultimately just sticking together existing (Intel) designs. Cut 'n paste if you will.

Still, this has some use in the Ultrabook and Tablet space where space itself is at a premium, battery life is king, and existing thermals are already questionable.

This has no business in the desktop or server world. It's evil. A stop-gap solution with massive tradeoffs.

 

[jeremyshaw]

It's basically an Atom with an optional high performance core attached, with all of the other benefits of Intel's Core platform (usually I/O).
The flipside is, it's basically an Atom with Core-level pricing, so...

This isn't innovation. This is copycatting a soon-to-be competitor's already proven concepts and ultimately just sticking together existing (Intel) designs. Cut 'n paste if you will.
[...]

Names, please.

 

[Absalom]

It's basically an Atom with an optional high performance core attached, with all of the other benefits of Intel's Core platform (usually I/O).
The flipside is, it's basically an Atom with Core-level pricing, so...


Names, please.

One is already mentioned in the article (hint: starts with a 'Q'). The fact that MS has been providing software developers with non-x86 compilers for quite some time hints that Windows, moving forward, is ready to embrace non-x86 designs. It's only a matter of time before those show up en masse. Probably start from the bottom of the stack and work their way upward. The premium segment, for now, has little worry.

 

[Nobu]

Yep, pretty much called it when they first announced stacking. There's almost no way to stack chips and not have issues with thermals, even if one (or most) of the chips in the stack are considerably lower power. It will take major cooling innovation to get around this roadblock, or else only stack the cold chips (but that has it's own downsides).

 

[Snowdog]

Yep, pretty much called it when they first announced stacking. There's almost no way to stack chips and not have issues with thermals, even if one (or most) of the chips in the stack are considerably lower power. It will take major cooling innovation to get around this roadblock, or else only stack the cold chips (but that has it's own downsides).

It would be fine if not for the POP memory. Otherwise the compute dies is on top and could be cooled easily. But the POP memory leaves a big air gap:

 

[Nobu]

It would be fine if not for the POP memory. Otherwise the compute dies is on top and could be cooled easily. But the POP memory leaves a big air gap:
View attachment 258444

Even without the POP memory, though, the small cores would get very hot from heat conducting via the copper interconnects. A HSF can conduct a lot of heat away, but not as quickly as direct copper/solder contact.

 

[Snowdog]

Even without the POP memory, though, the small cores would get very hot from heat conducting via the copper interconnects. A HSF can conduct a lot of heat away, but not as quickly as direct copper/solder contact.

Without the POP memory, the main die is on top which could then be in direct contact with a HSF, just like any other CPU die.

 

[Absalom]

Even without the POP memory, though, the small cores would get very hot from heat conducting via the copper interconnects. A HSF can conduct a lot of heat away, but not as quickly as direct copper/solder contact.

Anandtech's analysis of Notebookcheck's Lakefield numbers seems to indicate that the smaller cores isn't the problem. It's the big core. Either due to thermal or power budget constraints. And keep in mind there's only one of them.

Hence the conclusion that Lakefield is effectively just 4 Atom cores.

 

[Nobu]

Without the POP memory, the main die is on top which could then be in direct contact with a HSF, just like any other CPU die.

Right, but what I'm saying is it may still have to throttle to prevent damage to the interconnects or the small dies underneath, from heat leaking down off the big cores.

 

[Revdarian]

So, BIG.little 3d stacked. Yeap this is a proven solution for mobile /low power devices, it should work.

Edit : and right after saying that it should work I see the way they set it up and yeah it should but it won't. I guess that side by side is not going away for BIG.little

 

[defaultluser]

They castrated the singe Core in too many ways. You don have AVX 512 instruction support in Tremont, so this this defaults back to SSE4. They also don't support hyper-threading on Tremont, so they turned it off for this mess of a core.

When ARM designed big/little, they at least had the balls to keep the instruction sets and vector units support identical between the two.

So, it's 20% faster tha ARM in single thread, and sloewr at muilti-thread.

 

[sirmonkey1985]

One is already mentioned in the article (hint: starts with a 'Q'). The fact that MS has been providing software developers with non-x86 compilers for quite some time hints that Windows, moving forward, is ready to embrace non-x86 designs. It's only a matter of time before those show up en masse. Probably start from the bottom of the stack and work their way upward. The premium segment, for now, has little worry.

at the end of the day microsoft is a business so they're not going to limit their most important product to x86 only. since they dropped out of the cellphone market trying to get mobile windows on as many devices as they can is pretty damn important for them right now. don't expect x86 based windows to go anywhere anytime soon.

 

[DukenukemX]

So, BIG.little 3d stacked. Yeap this is a proven solution for mobile /low power devices, it should work.

Edit : and right after saying that it should work I see the way they set it up and yeah it should but it won't. I guess that side by side is not going away for BIG.little

I'm not a fan of this design as you could have 8 cores instead of a 4x4 setup where you only have 4 working cores at any given time. Instead of designing a core that can throttle down better and save the silicon.

 

[defaultluser]

I'm not a fan of this design as you could have 8 cores instead of a 4x4 setup where you only have 4 working cores at any given time. Instead of designing a core that can throttle down better and save the silicon.

They did this because they have no other option for keeping costs reasonable - Die size of Tiger lake is comparable to Zen 2 Renoir (and you get twice as many big cores in that 150mm Zen 2, and comparable APU).

The only way Intel can make a hybrid die affordable is if they cut tons of performance; that means cutting cores and major performance features!

Also, Ice Lake has such a shit performance curve, at 7w you'd still be stuck using these Tremont cores most o the time. That 7w target is the whole reason Intel threw this together.

 

[Revdarian]

If it could be possible yes that would be nice, but the thing is higher performance cores are inherently bigger /more complex to really achieve their goals(mainly prediction and cache iirc) and thus even throttling them harshly you are still "wasting" energy on the extra complexity/die area which is why they have instead gone for 2, and now up to 3, types of cores to properly fine tune performance per watt.
It is irksome for us to see "wasted silicon" in the way you get to use only a fraction of the whole soc at a time, but it fits their design goals of power efficiency over silicon efficiency.
Your approach would most likely give us cheaper performance/cost phones most likely since more silicon would be used at max but at reduced battery life even when only using it lightly.

 

[Red Falcon]

I'm not a fan of this design as you could have 8 cores instead of a 4x4 setup where you only have 4 working cores at any given time. Instead of designing a core that can throttle down better and save the silicon.

Yeah, I'm not a fan of heterogeneous CPU designs, either, and agree with just making an 8-core CPU, even with low-power CPU cores.
It made sense with ARM-based SoCs throughout the 2010s, but for x86-64, this is just more forced and unnecessary market segmentation by Intel to get their eggs into yet another basket.