Overclockers.com analysis: Prescott to be slower than Northwood

L

laja

Gawd
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An excerpt:

"After all, they're going to put out a CPU that will almost certainly be slower than its ancestor.

More importantly, if electrochemistry is causing all this problem, looks like they're stuck with it for at least a year."

http://www.overclockers.com/articles940/

Hmm... and the guy who wrote the article is no hardware newbie...
 
A lot of disquieting things are being said about it, presumably by those who are actually playing with the beast a little in advance.

...In a nutshell, what these statements boil down to is that the pipeline has allegedly been increased to thirty stages...
Click to expand...

This silly rumor is getting alot more attention than it deserves. However, this guy officially went off the deepend, making some rather extreme conclusons based on NOTHING.

But he introduces a new wrinkle.

Increasing the pipeline of Prescott from twenty to thirty stages at the last minute is a pretty (add expletive of your choice) desperate move by Intel. After all, the latest 130nm Northwoods don't fall all that short of the 4GHz goal right now. Historically, just a die-shrink ought to get Intel well over 4GHz with no fuss.
Click to expand...

He is smoking crack. You can't extend a pipeline by 50% at the 'last minute'... but that is not important.

More importantly, he didn't connect the dots and think: 'this is pretty good proof, if any proof was needed, that the '10 extra stages' rumor is wrong'.
 
http://www.hardforum.com/showthread.php?postid=1025631818#post1025631818

http://www.aceshardware.com/read_news.jsp?id=75000461
longer pipeline (fact)


http://www.pconline.com.cn/pchardware/tpylab/cpu/0401/298500.html
http://www.hkepc.com/hwdb/lga775-1.htm

<from hkepc.com>

Simultaneously under the arteries Prescott also is possibly slower than Northwood! ?

If must distinguish Prescott and the Northwood technical distinction, may say is the L1 & L2 Cache size, the SSE3 support, the Hyper-Threading improvement and most makes one dispute is Prescott increases to 32 Pipeline by former 20.

Actually CPU must increase the quick time arteries to be possible to obtain from two aspects &#65072; (1) in system regulation improvement (2) in technical improvement. But now the space which was allowed to improve in the system regulation already was not big, calculated further reduces the thin system regulation, but had to face the technical question had numerous number, for example produced the huge quantity of heat, produced the good rate question. But Intel in order to continue consistent Gao Shihmai policy, when the soldier &#34892;&#38570;, the use is enlarging CPU Pipeline Stage promotes the arteries.


Increases Pipeline the Stage by no means best good medicine

Why increases Pipeline Stage may increase when the arteries! ? First we must shallowly discuss the Pipeline principle, Prescott has 32Stage Pipeline, may divide into on behalf of CPU an instruction 32 to carry on, but each Mhz may operate two Stage, therefore 32Stage on probably needs 16Mhz (about reason work), but CPU may the identical time make ten several instructions, after but the new instruction needs to wait for on instruction Stage to complete can start, therefore if Stage obtains thin 1., namely each time arteries work the component can less also be able to complete as soon as possible, starts the next instruction, like this can be easier increases when the arteries.

But this theory is the supposition CPU work never makes a mistake can establish, but present CPU all is the use pays in advance the result (Branch Prediction) to increase the efficiency, but pays in advance the result is cannot 100% truest, when in 32 Stage if Stage makes a mistake, the work needs reto carry on, but other need obtain this to be connected this work instruction very to be also possible to have reto carry on, implicates and delays, less is bigger than Stage which Stage more pays in advance the result makes a mistake when makes.

When increases Stage makes the arteries and the potency can promote, the key lies in Branch Prediction the accuracy, but some Engineer CPU factory indicated must complete Branch Prediction is extremely difficult, whether 32 does Pipeline increase the potency must regard when the arteries increase obtained potency, whether or not eliminates because of pays in advance the result which the wrong detention brings.

But the author in some Intel release conference knew in under the identical time arteries, certain formulas transports the guild on Northwood to be more effective than Prescott, looked like is different sends as a result of the Pipeline number design, therefore simultaneously under the arteries 1MB L2 Cache Prescott unexpectedly is defeated, looked like increases the Pipeline number by no means best good medicine.
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The clockrate for Prescott would be much higher than for Northwood, who cares about IPC-Performance!?
 
Ed is an idiot. His analysis is shallow and very often wrong.
 
Yeah, and all the Intel zealots said AMD's little Hammer would stink, and they were wrong, weren't they? I don't think Intel would be this stupid - this would be exactly the stuff that let AMD get the drop on them last time around.
 
Originally posted by Tedinde
it's got to be fact if you read it somewhere or if someone posted it in a forum!!!!:D
Click to expand...
"longer pipeline (fact)"
is a quote from the article by aceshardware. :p

the link is to my own post in another thread. :D


imo the pipeline would be about 30 stages long, but if you have other information, i'll be very interested. :)
 
Too much guessing, and it will probably be slower than the current nw, Clock for clock im already counting on that.

Only way we will know is when one of us buys one.

I've got my credit card cocked and loaded. For a 2.8 and a 3.4.
 
I've been seeing a lot of this stuff lately. If so many places are saying this maybe it does have at least some credibility?

Personally, I won't believe anything until I see benchmarks on HardOCP, Tom's, or AnandTech. If the Prescott's are actually slower than the Northwood core, Intel is going to be in serious hot water. Like Nvidia was this time last year :).
 
No one is disputing that the Prescott has a longer pipeline. It has been said from over a year ago that there were around two extra stages, along with 1meg L2, PNI, improved HT, and all the other improvements we pretty much know are true.

The 10 extra stage rumor is just confusion over the different ways to count the number of stages in Northwood.

Prescott is 30 stages long only if you count Northwood as having 28 stages (which is technically correct depending on how you count the stages). To say Prescott has 10 extra stages is a totally unsubstantiated and IMO ridiculous rumor that was started recently, and not one credible source has called it anything other than a rumor of a rumor.
 
One thing is for sure about the Prescott, the prices are great. The 3.0Ghz Prescott is to be sold for $175. Great price for people looking to upgrade their older hardware to something newer.
 
Yeah, but will it be more cost effective than the AMD route?
 
I'm pretty sure Prescott was designed to have a longer pipeline.

From 28 to 32? (reports are sketchy at best)

Which means there is probably a slightly greater chance of a cache miss, and a slightly higher chance of a longer delay on a cache miss.

So clock for clock Mhz speed, if you don't include the larger cache and any other core optimizations that might have been added - The Prescott could and should be slower in certain instances.

Ed has gone off the deep end a few times, but he might have a point here.
 
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