vhdl question

[cdabc123]

Ive been trying to learn vhdl and havent been too successful in implementing modules that can interact with each other. The linked codes is for a top modual and bottom module (both vhdl) but I would also be interested in any tip on using a schematic as top or bottom module.

The bottom module is just suposed to flip a bit and the top should use that result to light a led


--top

library ieee;
use ieee.std_logic_1164.all;

-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;

-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity vhdl is



port(

RESET : in bit;
LED0,LED1,LED2,LED3,LED4,LED5,LED6,LED7 : out bit;
clock : in std_logic);


end vhdl;

architecture OR_arch of vhdl is


shared variable t : integer range 0 to 50000000;
shared variable t1 : integer range 0 to 255;
signal clk : bit;
signal clk1 : std_logic;
shared variable x : integer range 0 to 100000;
shared variable a : integer range 0 to 8;
shared variable b : std_logic_vector (0 to 8);
signal i1 : std_logic;
signal o1 : std_logic;


component bottom
     port(
i1 : out std_logic;
o1 : in std_logic);
end component;


     begin
 
    g1 : bottom port map (i1,o1);
 
 
     process(clock)
     begin
if rising_edge(clock) then
t:=t+1;
if (t=50000000) then
clk<=not clk;
clk1<=not clk1;
i1<=clk1;
o1<=clk1;
t:=0;
end if;
end if;
    end process;
 
     process(o1)
     begin
     if (o1='1') then
     led0<='1';
     else
     led0<='0';
     end if;
     end process;

end OR_arch;

--Bottom

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;

-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity bottom is
    Port ( o1 : out  std_logic;
           i1 : in  std_logic);
end bottom;

architecture Behavioral of bottom is
begin
process (i1)
begin
o1<= not i1;
end process;


end Behavioral;