Intel’s Take on the Next Wave of Moore’s Law

[kac77]

Intel’s Take on the Next Wave of Moore’s Law

Ann B. Kelleher explains what's new 75 years after the transistor's invention​

“Moore’s Law is about increasing the integration of functions,” says Kelleher. “As we look forward into the next 10 to 20 years, there’s a pipeline full of innovation” that will continue the cadence of improved products every two years. That path includes the usual continued improvements in semiconductor processes and design, but system technology co-optimization (STCO) will make the biggest difference.

 

[toast0]

Well, let's all hope their deep pipeline doesn't stall again.

 

[Red Falcon]

From the first article:

For example, Kelleher points out in her plenary that high-performance computing demands a large amount of cache memory per processor core, but chipmaker’s ability to shrink SRAM is not proceeding at the same pace as the scaling down of logic.

The memory issue, as presented here is going to be the next big hurdle, which is ironically enough presented in this video that asianometry just posted today.

 

[gvx64]

From the first article:

The memory issue, as presented here is going to be the next big hurdle, which is ironically enough presented in this video that asianometry just posted today.

Thanks for the video, the 3D memory concept is really interesting. That said, I can't imagine the heat issues that there will be if we start stacking memory layers on top of the CPU die (or even on the same chip). I am really curious what the plan will be to manage the thermals on the inner layers.

 

[Red Falcon]

Thanks for the video, the 3D memory concept is really interesting. That said, I can't imagine the heat issues that there will be if we start stacking memory layers on top of the CPU die (or even on the same chip). I am really curious what the plan will be to manage the thermals on the inner layers.

It is an interesting concept, and one that I'm surprised many industries have not adopted.
The original Raspberry Pi, back in 2012, used a POP stacked memory chip on top of the SoC, though granted that was a low-power single-core CPU and only a 256/512MB RAM chip on an SBC.

It does seem like a paradigm shift is going to be needed at some point to cut down on the latency, especially for supercomputers and other specialized compute equipment.

 

[Lakados]

Thanks for the video, the 3D memory concept is really interesting. That said, I can't imagine the heat issues that there will be if we start stacking memory layers on top of the CPU die (or even on the same chip). I am really curious what the plan will be to manage the thermals on the inner layers.

IBM and Intel partnered up on that a few years ago and this was the result of that work.
https://patents.google.com/patent/US20140071628A1/en

A package structure to implement two-phase cooling includes a chip stack disposed on a substrate, and a package lid that encloses the chip stack. The chip stack includes a plurality of conjoined chips, a central inlet manifold formed through a central region of the chip stack, and a peripheral outlet manifold. The central input manifold includes inlet nozzles to feed liquid coolant into flow cavities formed between adjacent conjoined chips. The peripheral outlet manifold outputs heated liquid and vapor from the flow cavities. The package lid includes a central coolant supply inlet aligned to the central inlet manifold, and a peripheral liquid-vapor outlet to output heated liquid and vapor that exits from the peripheral outlet manifold. Guiding walls may be included in the flow cavities to guide a flow of liquid and vapor, and the guiding walls can be arranged to form radial flow channels that are feed by different inlet nozzles of the central inlet manifold.


They have expanded on that work a lot over the last decade.

 

[noko]

IBM and Intel partnered up on that a few years ago and this was the result of that work.
https://patents.google.com/patent/US20140071628A1/en

A package structure to implement two-phase cooling includes a chip stack disposed on a substrate, and a package lid that encloses the chip stack. The chip stack includes a plurality of conjoined chips, a central inlet manifold formed through a central region of the chip stack, and a peripheral outlet manifold. The central input manifold includes inlet nozzles to feed liquid coolant into flow cavities formed between adjacent conjoined chips. The peripheral outlet manifold outputs heated liquid and vapor from the flow cavities. The package lid includes a central coolant supply inlet aligned to the central inlet manifold, and a peripheral liquid-vapor outlet to output heated liquid and vapor that exits from the peripheral outlet manifold. Guiding walls may be included in the flow cavities to guide a flow of liquid and vapor, and the guiding walls can be arranged to form radial flow channels that are feed by different inlet nozzles of the central inlet manifold.


They have expanded on that work a lot over the last decade.

AMD also researching this issue:
https://www.techpowerup.com/256902/amd-files-a-patent-for-cooling-of-3d-stacked-memory

A peltier device made with the chip.