Binned DDR5 supposedly hitting 10,000 MT/s

Mizzer said:
I don't understand RAM, timings, and Mega-super Hertz. I just find out which one works the best without any massaging from me. Install > Power on > good to go.
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That's how it works today, little one, but many moons ago, the [H]ardest among us would spend days and weeks running real-world and synthetic benchmarks on our tirelessly tweaked memory timings, only going to bed after loading up Prime95, and checking it for errors in the early dawn light -- if it made it through the dark hours.

For there was a time, once, when memory latency meant response time, and many frags depended on it, and we depended on the frags. It was gib or be gibbed, and we will never forget that time, even though it is long ago in our past.
 
Axman said:
That's how it works today, little one, but many moons ago, the [H]ardest among us would spend days and weeks running real-world and synthetic benchmarks on our tirelessly tweaked memory timings, only going to bed after loading up Prime95, and checking it for errors in the early dawn light -- if it made it through the dark hours.

For there was a time, once, when memory latency meant response time, and many frags depended on it, and we depended on the frags. It was gib or be gibbed, and we will never forget that time, even though it is long ago in our past.
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In enterprise, databases and services will suffer if someone sets memory timings improperly, so there are many real world use-case scenarios for this.
Increasing the data transfer rate for many-core CPUs is also a massive requirement which DDR4 can no longer accommodate.

DDR4 is fine for mobile to low-tier HEDT platforms, but beyond that DDR4 is starting to show its age, especially with 32+ CPU cores and multi-socket configurations, regardless of the ISA.
For the average user, though, you are correct.
 
I think a lot is being missed in this latency focus. DDR5 has a bunch of tweaks that make past metrics less comparable. Each DIMM is dual channel with on board circuitry with ECC and management. I only wonder if this can provide some out of order processing. The ROW latency (above) is only one factor.

If it takes an extra clock to manage 2 channels and ECC I can see where a 60/40 (3:2) ratio would work.

I never hang my hat on new memory technologies. The new requirements are certainly going to be pricey.
 
Every new generation of ram is slower than the standard speed of the previous gen at the time of release, it's always been this way. My 3200mhz cl14 2x 16gb kit of ram from 2017 will likely be considered an ok standard to compare ddr5 against when it comes out. It will be slower in most applications, but have higher mhz. This is why I have a 5950x and will be getting some good ram to go with my setup, and the first year or two of ddr5 won't be great, even considering the other improvements provided.
 
If any difference between DDR4 and DDR5 will make a noticeable difference for end users it'll be for people heavily loading high core count mainstream systems benefiting from each DDR5 channel being bifurcated, so that the system will effectively have 4 memory channels not 2.
 
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